1. Field of the Invention
The present invention relates in general to digital video signal processing and, more particularly, to improvements in video transcoding that reduce computation time.
2. Description of the Related Art
The present invention relates to the field of digital video signal processing. While definitions for selected terms in the field of digital video signal processing used herein are provided, a more complete set of definitions for this field of art is provided in International Standard ISO/IEC 13818-2 entitled xe2x80x9cInformation technology-Generic coding of moving pictures and associated audio information: Video,xe2x80x9d dated May 15, 1996, and ITU-T Rec. H.263 entitled xe2x80x9cVideo coding for low bit-rate communication,xe2x80x9d dated May 1997, which are incorporated in their entirety herein by reference. Also, the general requirements and operations of a video encoder are disclosed in Sun et al., xe2x80x9cStatistical Computation of Discrete Cosine Transform in Video Encoders,xe2x80x9d Journal of Visual Communications and Image Representation, Vol. 9, No. 2, pp. 163-170, June, 1998, which is incorporated in its entirety herein by reference.
Transcoding as used herein refers to an operation of decoding into the pixel domain an incoming encoded compressed video signal, and then re-encoding the decoded video signal into an encoded signal having a desired bit rate or format. Such transcoding enables, for example, converting an incoming video signal at a given bit rate into another data stream having a different bit rate. A more specific example of an application of transcoding is to convert the bit rate of an MPEG compressed video signal at, e.g., 9 Mbit/sec, to a lower bit rate so the signal can be relayed at a cable head with a limited capacity and lower bit rate.
FIG. 1 illustrates a cascaded pixel domain transcoder architecture 100 that includes a decoder section 102 and an encoder section 104. Decoder section 102 includes a block 110 for performing an inverse quantization (IQ) on an incoming bit stream from a front-encoder (not shown) and a block 112 for performing an inverse discrete cosine transform (IDCT) on the output of block 110. Block 112 outputs the decoded bit stream which is applied to a first input of a summer 114. Motion compensation of the decoded bit stream is performed by a frame buffer (F) 116 and a motion compensation (MC) unit 118 coupled between a sum output and a second input of summer 114 and also coupled to receive motion vectors (MV).
Encoder section 104 includes a summer 120 having a first input coupled to receive the decoded and motion compensated bit stream from decoder section 102. A block 122 performs a discrete cosine transform (DCT) on a sum output of summer 120. The output of block 122 is applied to a block 124 which performs a quantization (Q) thereon. The output of block 124 is the encoded output of encoder section 104 and transcoder 100. The encoded output is ultimately intended for receipt by an end-decoder (not shown).
Motion compensation of the encoded output of encoder section 104 is performed by a block 126 for performing an IQ, a block 128 for performing an IDCT, a summer 130, a frame buffer (F) 132 and a motion compensation unit (MC) 134, all coupled between the output of block 124 and a second input of summer 120. Unit 134 is coupled to receive motion vectors (MV).
A direct implementation of transcoder 100 is to fully decode an incoming compressed bit-stream into the pixel-domain and then re-encode the decoded video into the desirable bit-rate. The cascaded pixel-domain transcoder architecture of transcoder 100 is flexible, since decoder 102 and encoder 104 can be totally independent of each other. For example, decoder 102 and encoder 104 can operate at different bit rates, picture resolutions, coding modes, and even according to different standards. The architecture can be implemented to achieve drift-free operation if the implementations of IDCT in the front-encoder and the end-decoder are known. In such a case, the decoder loop and the encoder loop can be implemented to produce exactly the same reconstructed pictures as those in the front-encoder and the end-decoder, respectively. Alternatively, if the implementations of the IDCTs in the front-encoder and end-decoder are not known, drift will not be significant, as long as the IDCT implementations satisfy IEEE Standard No. 1180-1990, which provides specifications for implementation of the IDCT, and macroblocks are refreshed as specified in other standards covering coding and communication of video signals, including the above-cited ISO/IEEE 13818-2 and ITU-T Rec. H.263. Since several coding parameters such as coding modes and motion vectors can be reused, the overall complexity of the architecture is not as high as the sum of a decoder and an encoder. However, the architecture is still computationally expensive.
To reduce the complexity of the cascaded pixel-domain transcoder architecture, several fast architectures have been proposed. For example, Eleftheriadis et al., xe2x80x9cConstrained and general dynamic rate shaping of compressed digital video,xe2x80x9d Proc. IEEE Int. Conf. Image Processing, Washington, D.C., October 1995, discloses an open-loop transcoder in which bit-rate adaptation is achieved by requantizing or truncating the DCT coefficients. Since the transcoding is carried out in the coded domain, where complete decoding and re-encoding is not required, the open loop transcoder can achieve fast operation. However, open-loop transcoding can produce significant quality degradation caused by drift due to mismatched reconstructed pictures between the front-encoder and the end-decoder.
To achieve less computation than the cascaded pixel-domain transcoder and better video quality than the open-loop transcoder, several other fast architectures have been proposed. Based on the assumptions that motion compensation (MC) and DCT/IDCT are linear operations, and a DCT will cancel out an IDCT (assuming the accuracy of DCT/IDCT operations is infinite), a fast transcoder architecture can be derived from the cascaded pixel-domain transcoder. FIG. 2 illustrates the architecture of one such fast transcoder 200 disclosed in Keesman et al., xe2x80x9cTranscoding of MPEG bitstream,xe2x80x9d Signal Proc.: Image Commun., pp. 481-500, 1996. In FIG. 2, the functional acronyms within the blocks designate the same general functions as described above for FIG. 1. The architecture in FIG. 2 is based on the assumption that the same motion vectors and coding modes are present in the decoder and the encoder of the cascaded transcoder architecture so that they can be combined into one loop.
In FIG. 2, the DCT and IDCT are needed only for motion compensation performed in the pixel-domain. Therefore, if the motion compensation can be performed in the DCT domain, the architecture of a transcoder 300 illustrated in FIG. 3 can be implemented as discussed in Assunxc3xa7ao et al., xe2x80x9cA frequency-domain video transcoder for dynamic bit-rate reduction of MPEG-2 bit streams,xe2x80x9d IEEE Trans. On Circuits Syst. Video Technol., Vol. 8, No. 8, pp. 953-967, 1998. This architecture is also disclosed in the above-cited Assunxc3xa7ao et al. reference and is referred to herein as the DCT domain transcoder. Thus, the DCT domain transcoder is configured by making substantial changes to cascaded pixel-domain transcoder architecture.
It would, however, be desirable to reduce the computational complexity of the cascaded pixel-domain transcoder architecture by means of less substantial changes in order to assure that the high picture quality this architecture provides is maintained.
Accordingly, the present invention is directed to a transcoder and methods of transcoding that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
Additional features and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the apparatus and methods particularly pointed out in the written description and claims hereof as well as the appended drawings. To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention is directed to a method for transcoding coded digital video signals representing blocks of pixels, comprising the steps of: decoding inputted encoded digital signals, including the steps of determining an end-of-block (EOB) position in an incoming block of the encoded inputted signal, inverse quantizing the inputted signals, determining a discrete cosine transform (DCT) block type based on the EOB position, and performing partial inverse DCT computations based on the DCT block type to provide decoded signals; and encoding the decoded signals, including the steps of determining if an incoming block of the decoded signals is intracoded or intercoded, performing a DCT of the decoded signals by selecting, if the incoming block is intracoded, DCT coefficients from the inverse quantized inputted signals to provide transformed signals, and performing a DCT of the decoded signal by computing, if the incoming block is intercoded, selected DCT coefficients located before the EOB position of the incoming block to provide transformed signals.
Also in accordance with the present invention there is provided a method for transcoding coded digital video signals representing blocks of pixels, comprising the steps of: decoding inputted encoded digital signals, including steps of determining an end-of-block (EOB) position in an incoming block of the encoded inputted signal, inverse quantizing the inputted signals, determining a discrete cosine transform (DCT) block type based on the EOB position, and performing partial inverse DCT computations based on the DCT block type to provide decoded signals; and encoding the decoded signals.
Further in accordance with the present invention there is provided a method for transcoding coded digital video signals representing blocks of pixels, comprising the steps of: decoding inputted encoded digital signals, including steps of determining an end-of-block (EOB) position in an incoming block of the encoded inputted signal prior to inverse quantizing, inverse quantizing the inputted signals, and encoding the decoded signals, including steps of determining if an incoming block of the decoded signals is intracoded or intercoded, performing a discrete cosine transform (DCT) of the decoded signals by selecting, if the incoming block is intracoded, DCT coefficients from the inverse quantized inputted signals to provide transformed signals, and performing a DCT of the decoded signal by computing, if the incoming block is intercoded, selected DCT coefficients located before the EOB position of the incoming block to provide transformed signals.
Additionally in accordance with the present invention there is provided a transcoder for transcoding coded digital video signals representing blocks of pixels, comprising: a decoder for decoding inputted coded digital signals, including means for determining an end-of-block (EOB) position in an incoming block of the encoded inputted signal, an inverse quantizer for inverse quantizing the inputted signals, means for determining a discrete cosine transform (DCT) block type based on the EOB position, and an inverse discrete cosine transformer for performing partial inverse DCT computations based on the determined DCT block type to provide decoded signals; and an encoder to encode the decoded signals.
Yet further in accordance with the present invention there is provided a transcoder for transcoding digital video signals representing blocks of pixels, comprising: a decoder for decoding inputted encoded digital signals, including means for determining an end-of-block (EOB) position in an incoming block of the encoded inputted signals; and an inverse quantizer for inverse quantizing the inputted signal, and an encoder to encode the decoded signals, the encoder including means for determining if an incoming block of the decoded signals is intracoded or intercoded, and a discrete cosine transformer for performing a discrete cosine transform (DCT) of the decoded signals by selecting, if the incoming block is intracoded, DCT coefficients determined from the inverse quantized inputted signals, the discrete cosine transformer performing the DCT by computing, if the incoming block is intercoded, selected DCT coefficients located before the EOB position of the incoming block.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate an embodiment of the invention and together with the description serve to explain principles of the invention.